1. Field of the Invention
The present invention relates to a method for forming SiGe bipolar transistor, and especially relates for a method for forming SiGe bipolar transistor that utilized in high frequency circuit with lowered thermal budget.
2. Description of the Prior Art
Because of the characteristic of the bipolar transistor, and the signal processed by the transistor in the radio frequency circuit is a signal having high frequency, the bipolar transistor, especially the SiGe bipolar transistor, is frequently employed in the radio frequency circuit. However the traditional SiGe bipolar transistor manufacturing process has many disadvantages such as low yield resulting from the low growth rate of the epitaxial growth process. In addition, in the traditional method, the epitaxial growth process is utilized two times when fabricating the SiGe bipolar transistor. The first epitaxial growth process is used to fabricate the collector layer, which is about 1 micron in thickness, and the second epitaxial growth process is used to form the epitaxial base layer. Because the epitaxial growth process takes a lot of time, thus the two epitaxial growth processes utilized by the traditional SiGe bipolar transistor manufacturing process take much more time, and take longer cycling time as well as lower yield.
In addition, before epitaxially grow the SiGe layer, it is necessary to proceed with the wafer, which is very troublesome. Also, it tends to waste manufacturing time and result lower yield to some extent. At first, the process sequence employed to manufacture the heterojunction bipolar transistor (HBT) is described to illustrate how a SiGe bipolar transistor is fabricated via the traditional process.
As shown in FIG. 1A, the first step is to form a P type epitaxial layer 10 on a silicon substrate 11, and the next step is to form a n+ buried layer 12 on the P type epitaxial layer 10 by an implanting step. Followed by the foregoing implanting step, a nxe2x88x92 epitaxial layer 14 is formed on the n+ buried layer 12 by a first epitaxial growth step, which is controlled at the temperature from about 1000 to 1200 degrees in centigrade scale. Subsequently use a first photography step and a first etching step to etch the nxe2x88x92 epitaxial layer 14 and then define the trench in the n+ buried layer 12 and the P type epitaxial layer 10, which exposing a portion of the silicon substrate 11. The concentration of the conductive carrier in the nxe2x88x92 epitaxial layer 14 is designed to be that of the collector of the SiGe bipolar transistor. The etched nxe2x88x92 epitaxial layer 14 includes the first area 14a having a first cave and the second area 14b having a second cave.
The first area 14a is defined as the active area of the transistor that will be fabricated in the following processes, and the second area 14b is defined as the collector of the transistor that will be fabricated in the following processes. The next step is to form the trench isolation 16, which comprised of polysilicon portion 16a and oxide portion 16b at the interior surface of the trench at the bottom of both the first cave and the second cave. The silicon dioxide is then filled into the first cave in the etched portion of the nxe2x88x92 epitaxial layer 14, so the first silicon dioxide pattern 18a is formed in the first area 14a of the nxe2x88x92 epitaxial layer 14. In addition, the second silicon dioxide pattern 18b is formed in the second area 14b of the nxe2x88x92 epitaxial layer 14.
After the active area and collector of the transistor have been defined, base of the transistor is to be defined in the following processes. However, a layer of native oxide is always expectedly formed on the surface of the first area 14a and the second area 14b of the nxe2x88x92 epitaxial layer 14. Due to the unavoidable formation of the native oxide layer 22 on the nxe2x88x92 epitaxial layer 14, referring to FIG. 1B, the first polysilicon layer 25 is formed on the native oxide layer 22. The wafer having the native oxide layer 22 on the second area 14b of the nxe2x88x92 epitaxial layer 14 is immersed into HF to remove the exposed native oxide layer. It is important that the wafer must be directly sent to the tube which growing the GeSi epitaxial layer 30 (referring to FIG. 1C) without any cleaning step using water. The transmission of the wafer had been immersed into the HF is very dangerous for the operator, and a layer of several angstroms of native oxide layer 22 on the surface of the first area 14aof the nxe2x88x92 epitaxial layer 14 still exist after the etching process using HF. Though the residual native oxide layer 22 is not shown in FIG. 1B and FIG. 1C, it still exist between the GeSi epitaxial layer 30 and the first area 14a of the nxe2x88x92 epitaxial layer 14. So the yield of fabricating SiGe bipolar transistor using prior art is relatively lowered, and the cycling time is increased because the GeSi epitaxial layer 30 is formed by a second epitaxial growth process is controlled under about 550 degrees in centigrade scale.
The GeSi epitaxial layer 30 mentioned above is designed as the base of the SiGe bipolar transistor that is to be fabricated in the following processes, in addition, the SiGe bipolar transistor is usually employed in the high frequency circuit. So the concentration of the carrier and the thickness of the base of the SiGe bipolar transistor must be very carefully controlled.
After the GeSi epitaxial layer 30 had been formed on the surface of the second area 14b of the nxe2x88x92 epitaxial layer 14, the first polysilicon layer 25 is transferred into the polycrystalline GeSi layer 35. Next, refer to FIG. 1D, a first silicon nitride layer 38 and a second polysilicon layer 40 are subsequently formed on the GeSi epitaxial layer 30 and the polycrystalline GeSi layer 35. In order to define the base of the transistor, a second silicon nitride layer 42 and a silicon dioxide layer 44 are subsequently formed on the second polysilicon layer 40 followed by patterning them. So the patterned second silicon nitride layer 42 and the patterned silicon dioxide layer 44 are formed on the surface of the second polysilicon layer 40 in the first area 14a. 
Then an implantation step is utilized to form the P+ region, besides, an oxidation step is utilized to proceed with the wafer, so the portion of the second polysilicon layer 40 without coverage from the patterned second silicon nitride layer 42 are transformed to the third silicon dioxide layer 46 as shown in FIG. 1E. In addition, the P+ region is driven deeper into the nxe2x88x92 epitaxial layer 14. Subsequently, as shown in FIG. 1E, the patterned second silicon dioxide layer 44 is removed, and the patterned second silicon nitride layer 42 is exposed. Followed by etching the patterned second silicon nitride layer 42, a portion of the first silicon nitride layer 38 was covered by the remaining second polysilicon layer 40 and the remaining second polysilicon layer 40 are removed, as shown in FIG. 1F, and a portion of the GeSi epitaxial layer 30 is exposed.
Followed by subsequently forming a n+ polysilicon layer 50 and a third silicon nitride layer 52 on the exposed portion of GeSi epitaxial layer 30, a photolithography step and an etching step are employed to define the n+ polysilicon layer 50, the third silicon nitride layer 52, and the third silicon dioxide layer 46, thus forming the patterned n+ polysilicon layer 50 and the patterned third silicon nitride layer 52 as shown in FIG. 1G. Besides, a portion of the third silicon dioxide layer 46 covered by the patterned n+ polysilicon layer 50 still remained after the foregoing etching step. The patterned n+ polysilicon layer 50 composed the emitter of the SiGe bipolar transistor.
Next, a photolithography step and an etching step are employed to etch a portion of the first silicon nitride layer 38, the polycrystalline GeSi layer 35 to the native oxide layer 22, a portion of the second silicon dioxide pattern 18b, and a portion of the first silicon dioxide pattern 18a are exposed as shown in FIG. 1H. The patterned silicon nitride layer 38 and the patterned polycrystalline GeSi layer 35 are electrically coupled to the base of the SiGe bipolar transistor. Besides, the nxe2x88x92 epitaxial layer 14 in the second area 14b is electrically coupled to the collector of the SiGe bipolar transistor.
According to the prior art, the nxe2x88x92 epitaxial layer 14 and the GeSi epitaxial layer 30 are not formed insitu, so the quality of the base of the SiGe bipolar transistor is easily out of control. In order to remove the native oxide layer resulted from the reason mentioned above, the operator is obliged to use HF to clean the wafer before forming the base of the SiGe bipolar transistor. In addition, the cleaning step can not thoroughly remove the native oxide layer before forming the GeSi epitaxial layer (base). So the prior art takes more time to preclean the wafer so as to remove the any impurity and native oxide at the surface and must carefully deposit the SiGe base layer in order to assure the good quality, especially that utilized in high frequency circuit.
A method for fabricating bipolar transistor frequently used in high frequency circuit is disclosed herein. The foregoing method employed to fabricate an epitaxial base bipolar transistor includes the following steps. According to one preferred embodiment of the present invention, the first step is to form a buried layer having a first conductivity in a substrate, and then the following step is to form a first oxide layer on the buried layer. Next, pattern the first oxide layer to expose a portion of the buried layer and use a first epitaxial process to selectively grow a epitaxial collector layer in the etched first oxide layer to cover the exposed portion of buried layer. Immediately use a second epitaxial process to subsequently grow a first epitaxial-base layer and a second epitaxial-base layer on the epitaxial collector layer and the etched portion of first oxide layer. The second epitaxial-base layer is formed on the first epitaxial-base layer, especially, the second epitaxial process and the first epitaxial process are performed insitu.
Subsequently, a TEOS layer is formed on the second epitaxial-base layer, and then patterned to expose a first portion of the second epitaxial-base layer. Next, form a poly emitter layer on the first portion of the second epitaxial-base layer and the TEOS layer. The next step is to pattern the poly emitter layer and the TEOS layer to expose a second portion of the second epitaxial-base layer. Then implant the second portion of the second epitaxial-base layer to form extrinsic base of the bipolar transistor in the second portion of the second epitaxial-base layer. Subsequently, pattern the second portion of the second epitaxial-base layer and the first epitaxial-base layer to expose a portion of the first oxide layer. The patterned second portion of the second epitaxial-base layer together with the etched first epitaxial-base layer make up the epitaxial base of the bipolar transistor, the patterned poly emitter layer composes the emitter of the bipolar transistor, and the epitaxial collector layer on the buried layer make the collector of the bipolar transistor.
The foregoing substrate is of the sheet resistance about 15-25 Ohms-cm. When the buried layer is formed using Sb as dophant source, the implanting energy is about 50 to 100 KeV, the concentration of the dophant is about 1E15 to 2E16. At this situation, the buried layer is disposed in 1150-1250xc2x0 C. for about 60-120 minutes. When the buried layer is formed using As as dophant source, the implanting energy is about 50 to 100 KeV, the concentration of the dophant is about 1E15 to 2E16. At this situation, the buried layer is disposed in 1100-1200xc2x0 C. for about 60-120 minutes. The foregoing buried layer is annealed to enlarge depth of the first doped region to a depth more than 1 micron. The first oxide layer and the epitaxial collector layer are of the thickness about 1000-5000 angstroms, wherein the epitaxial collector layer is formed containing boron of concentration about 1E15 to 5E17 cmxe2x88x923. The first epitaxial-base layer mentioned above is made of epitaxial SiGe, wherein the Ge composition is about 0-30%, and boron is utilized as dopant, the concentration of boron is about 1E18 to 1E20cmxe2x88x923. The second epitaxial-base layer is about 200 angstroms in thickness, and the sheet resistance of the second epitaxial-base layer is about 0.5 Ohms-cm.
According to the other preferred embodiment of the present invention, the first step is to form a buried layer having a first conductivity in a substrate, and then the following step is to form a first oxide layer on the buried layer. Next, pattern the first oxide layer to expose a portion of the buried layer and use a first epitaxial process to selectively grow a epitaxial collector layer in the etched first oxide layer to cover the exposed portion of buried layer. Then use an insitu second epitaxial process to subsequently grow a first epitaxial-base layer, a second epitaxial-base layer, and a third epitaxial-base layer on the epitaxial collector layer and the etched portion of first oxide layer. The second epitaxial-base layer is formed on the first epitaxial-base layer, the third epitaxial-base layer is formed on the second epitaxial-base layer. Particularly the second epitaxial process and the first epitaxial process are performed insitu.
Then a TEOS layer is formed on the third epitaxial-base layer, a first silicon nitride layer is formed on the TEOS layer. Pattern the first silicon nitride layer, the TEOS layer, the third epitaxial-base layer, the second epitaxial-base layer, and the first epitaxial-base layer to expose a portion of the first oxide layer. Subsequently, etch a portion of the patterned first silicon nitride layer, the TEOS layer, the third epitaxial-base layer, and the second epitaxial-base layer to expose a portion of the first epitaxial-base layer. Then anneal the expose portion of the first epitaxial-base layer to form a sacrifical oxide layer on the exposed portion of the first epitaxial-base layer, and remove the sacrifical oxide layer to expose a portion of the first epitaxial-base layer. Next a pad oxide layer is formed on the exposed portion of the first epitaxial-base layer.
Subsequently, form a second silicon nitride layer on the etched first silicon nitride layer, on the surface of the pad oxide layer, on the side-wall of the patterned TEOS layer, the patterned third epitaxial-base layer, the patterned second epitaxial-base layer, and the patterned first epitaxial-base layer. Then form a first polysilicon layer on the topography of the second silicon nitride layer. Then etch the first polysilicon layer to form a polysilicon spacer on sidewall of a portion of the second silicon nitride layer underlying the pad oxide layer. Etching the second silicon nitride layer to expose the first silicon nitride layer and a portion of the pad oxide layer, and then etch the exposed portion of the pad oxide layer to expose a part of the exposed portion of the first epitaxial-base layer.
Next, form a second polysilicon layer on the first oxide layer, the first silicon nitride layer, the polysilicon spacer, and the part of the exposed portion of the first epitaxial-base layer. Then implant a plurality of charges into the second poly-silicon layer. Subsequently, pattern the second polysilicon layer to expose the exposed portion of the first oxide layer, and a portion of the patterned first silicon nitride layer. The patterned second polysilicon layer makes up the emitter of the bipolar transistor, the patterned first epitaxial-base layer composes the intrinsic base of the bipolar transistor. The patterned third epitaxial-base layer, and the patterned second epitaxial-base layer composes extrinsic base of the bipolar transistor, the intrinsic base and the extrinsic base composes the base of the bipolar transistor. The epitaxial collector layer on the buried layer makes up the collector of the bipolar transistor.
In the other preferred embodiment of the present invention, the foregoing substrate is of the sheet resistance about 15-25 Ohms-cm. When the buried layer is formed using Sb as dopant source, the implanting energy is about 50 to 100 Kev, the concentration of the dopant is about 1E15-2E16 cm2. At this situation, the buried layer is disposed in 1150-1250xc2x0 C. for about 60-120 minutes. When the buried layer is formed using As as dopant source, the implanting energy is about 50 to 100 Kev, the concentration of the dopant is about 1E15 to 2E16 cm2xe2x88x92. At this situation, the buried layer is disposed in 1100-1200xc2x0 C. for about 60-120 minutes. The foregoing buried layer is annealed to enlarge depth of the first doped region to a depth more than 1 micron. The first oxide layer and the epitaxial collector layer are of the thickness about 1000-5000 angstroms, wherein the epitaxial collector layer is formed containing boron of concentration about 1E15 to 5E17 cmxe2x88x922. The first epitaxial-base layer mentioned above is made of epitaxial SiGe, wherein the Ge composition is about 0-30%, and boron is utilized as dopant, the concentration of boron is about 1E18 to 1E20 cmxe2x88x923. The second epitaxial-base layer is made of P-type Si, the concentration of the dopant in the P-type Si is about 5E20cmxe2x88x923. The third epitaxial-base layer is made of undoped Si about 100 angstroms in thickness. A time mode etching process is utilized to etch a portion of the patterned first silicon nitride layer, the TEOS layer, the third epitaxial-base layer, and the second epitaxial-base layer.